Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLASep 1, 2020ยทWen Wang,Shanquan Tian,Bernhard Jungk,Nina Bindel,Patrick Longa,Jakub Szeferยท 0 min read PDF CiteTypePaperPublicationIACR transactions on cryptographic hardware and embedded systemsLast updated on Sep 1, 2020 ← Remote power attacks on the versatile tensor accelerator in multi-tenant FPGAs (Best Paper Candidate) Feb 1, 2021Fingerprinting Cloud FPGA Infrastructures Feb 1, 2020 →