Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA9月 1, 2020·Wen Wang,Shanquan Tian,Bernhard Jungk,Nina Bindel,Patrick Longa,Jakub Szefer· 0 分钟阅读时长 PDF 引用类型Paper出版物IACR transactions on cryptographic hardware and embedded systems最近更新于 9月 1, 2020 ← Remote power attacks on the versatile tensor accelerator in multi-tenant FPGAs (Best Paper Candidate) 2月 1, 2021Fingerprinting Cloud FPGA Infrastructures 2月 1, 2020 →